1. Field of the Invention
The present invention relates to a shift circuit performing shift operation for sequentially shifting an applied signal in synchronization with a clock signal and a synchronous semiconductor memory device using the same, and more particularly to a shift circuit capable of reducing power consumption and a synchronous semiconductor memory device using the same.
2. Description of the Background Art
A shift circuit transferring an applied signal/data by shift operation in synchronization with a clock signal is used in various semiconductor devices. The shift circuit is used for example in a parallel/serial conversion circuit converting parallel data to serial data and in a delay circuit delaying a signal by a prescribed time.
Such a shift circuit is also used in a synchronous semiconductor memory device operating in synchronization with a clock signal in order to determine internal operation timing using the clock signal as a reference. The shift circuit used in the synchronous semiconductor memory device will now be described.
FIG. 13 schematically shows an overall arrangement of a conventional synchronous semiconductor memory device. Referring to FIG. 13, the synchronous semiconductor memory device includes: a memory cell array 1 having a plurality of memory cells arranged in a matrix of rows and columns; a row selection circuit 3 receiving an internal row address signal X applied from an address buffer 2 to drive the row in memory cell array 1 designated by the internal row address signal X; a column selection circuit 4 selecting, in accordance with an internal column address signal Y applied from address buffer 2, the column in memory cell array 1 designated by the column address signal Y; a sense amplifier sensing and amplifying data of a memory cell connected to a selected row in memory cell array 1; and an IO gate connecting the selected row in memory cell array 1 to an internal data bus in accordance with a column selection signal from a column selection circuit 4. The sense amplifier and the IO gate are shown in a single block 5 in FIG. 13.
Row selection circuit 3 includes a row address decoder for decoding the applied row address signal, and a word line drive circuit for driving the selected row in memory cell array 1 into a selected state in accordance with an output signal from the row address decoder. Column selection circuit 4 includes a column decoder decoding the applied internal column address signal Y to produce a column selection signal, and a burst address generator sequentially generating an internal column address signal in a prescribed sequence in synchronization with an internal clock signal CLK for transmission to the column decoder.
Address buffer 2 receives externally applied address signal bits A0 to An in synchronization with internal clock signal CLK to produce internal address signals X and Y.
The synchronous semiconductor memory device further includes an input/output circuit 6 for data input/output. Input/output circuit 6 generally includes: an input buffer receiving externally applied write data to generate internal write data; a write driver amplifying the internal write data from the input buffer for transmission to a selected memory cell; a preamplifier amplifying data read out from the selected memory cell; and an output buffer further performing buffering for the data from the preamplifier for external output.
The synchronous semiconductor memory device further includes: an input buffer circuit 7 receiving a control signal, that is, an external row address strobe signal extZRAS, an external column address strobe signal extZCAS and an external write enable signal extZWE externally applied in synchronization with internal clock signal CLK to generate an internal row address strobe signal RAS, an internal column address strobe signal CAS and internal write enable signal WE; a command decoder 8 determining the states of signals RAS, CAS and WE from input buffer circuit 7 and generating a signal for designating an operation mode in accordance with the determination result; a row related control circuit 9 activated in response to a row selection operation designation signal from command decoder 8, to perform control necessary for row selection operation; a column related control circuit 10 activated in response to a column selection operation designation signal from command decoder 8, to perform control necessary for column selection operation; and an input/output control circuit 11 driven in response to a data input/output operation designation signal from command decoder 8, to perform an operation necessary for data input/output.
Row related control circuit 9 controls activation/inactivation of row selection circuit 3, and also controls activation/inactivation of the sense amplifier included in block 5. Column related control circuit 10 controls operation of column selection circuit 4 and input/output control circuit 11 controls operation of an input/output circuit. Although not clearly shown in FIG. 13, address buffer 2 incorporates and latches an applied address signal in accordance with an address latch designation signal from row related control circuit 9 and column related control circuit 10 to produce internal row address signal X and internal column address signal Y.
The synchronous semiconductor memory device further includes: a clock input buffer 12 receiving an externally applied clock signal extCLK to produce an internal clock signal CLK; a clock generation circuit 13 enabled upon activation of a clock activation designation signal from row related control circuit 9, to produce a column related clock signal CLKD in accordance with internal clock signal CLK from clock input buffer 12; a DQM buffer 14 receiving an externally applied mask designation signal extDQM to produce a mask designation signal DQMIN in synchronization with internal clock signal CLK; and a mask control circuit 15 incorporating mask designation signal DQMIN in synchronization with internal clock signal CLK, to output internal mask designation signal DQMOT.
Clock generation circuit 13 is activated when row related control circuit 9 receives a row related selection operation designation signal for row selection operation from command decoder 8, as the application of the row related selection operation designation signal is followed by the application of a column selection operation designation signal for data writing/reading. Internal clock signal CLKD from clock generation circuit 13 is applied to column related control circuit 10 and input/output control circuit 11. Input/output control circuit 11 also receives internal mask designation signal DQMOT from mask control circuit 15.
FIG. 14 is a diagram showing an arrangement of the portion related to data reading of the synchronous semiconductor memory device shown in FIG. 13. In FIG. 14, an arrangement of command decoder 8, input/output control circuit 11, DQM buffer 14, mask control circuit 15 and input/output circuit 6 is shown.
Referring to FIG. 14, command decoder 8 includes a read command decoder 8a which receives negative logic signals /RAS, /CAS and /WE applied from an input buffer circuit 7 shown in FIG. 13, and determines that a read command of designating data reading is applied when these signals are set in prescribed states at the rising edge of internal clock signal CLK, to drive a data reading designation signal .phi.r into an active state.
An operation mode instruction is applied in the form of a command in the synchronous semiconductor memory device. More specifically, the operation mode is designated in accordance with a combination of the states of signals /RAS, /CAS and /WE. The read command is applied when row address strobe signal /RAS is set to at H level and column address strobe signal /CAS and write enable signal /WE are both set at L level at the rising edge of internal clock signal CLK. Upon application of the read command, read command decoder 8a drives data read operation designation signal .phi.r into the active state for a prescribed time in synchronization with internal clock signal CLK.
Input/output control circuit 11 includes: a read control circuit 11a activated in response to activation of read operation designation signal .phi.r from read command decoder 8a, to operate in synchronization with a column related internal clock signal CLKD from clock generation circuit 13 shown in FIG. 13 to output a preamplifier activation signal PAE and a data output designation signal OEMF; a latency shifter 11b operating in synchronization with column related internal clock signal CLKD and delaying data output designation signal OEMF from read control circuit 11a by a prescribed period of time to output a data output activation signal OEM; and an output control circuit 11c outputting an output enable signal OEMD for enabling data output in accordance with internal mask designation signal DEMOT from mask control circuit 15 and data output activation signal OEM from latency shifter 11b.
Read control circuit 11a includes a counter and drives preamplifier activation signal PAE into the active state in synchronization with column related internal clock signal CLKD. The number of times of activation for preamplifier activation signal PAE is determined by the counter included in read control circuit 11a. The counter normally counts a burst length. Here, the burst length represents the number of data successively read or written when one access command (either a read command or a write command for designating reading/writing of data) is applied. The data output designation signal OEMF is also driven into the active state in accordance with activation of read operation designation signal .phi.r for the period of the burst length.
Latency shifter 11b normally delays data output designation signal OEMF by a period of CAS latency minus one clock cycle for output. Here, CAS latency represents the number of clock cycles required for external output of valid data upon application of the read command. Latency shifter 11b is normally structured with a shift circuit, and shifts data output designation signal OEMF in accordance with column related internal clock signal CLKD to output data output activation signal OEM.
Output control circuit 11c sets output enable signal OEMD in the inactive state when internal mask designation signal DQMOT is designating mask for the read out data, and outputs internal enable signal OEMD in accordance with data output activation signal OEM when internal mask designation signal DQMOT is in the inactive state and not designating mask for the read out data.
Input/output circuit 6 includes a preamplifier 6a activated in response to activation of preamplifier activation signal PAE from read control circuit 11a, for amplifying the data of the selected memory cell in memory cell array 1 and an output buffer 6b for buffering the data applied from preamplifier 6a upon activation of output enable signal OEMD for external output. Output buffer 6b is brought into an output high impedance state upon inactivation of output enable signal OEMD.
A mask control circuit 15, whose structure will be later described in detail, delays mask designation signal DQMIN applied from a DQM buffer 14 by shift operation in synchronization with internal clock signal CLK to output internal mask designation signal DQMOT. The operation of the synchronous semiconductor memory device shown in FIGS. 13 and 14 during data reading will now be described with reference to a timing chart shown in FIG. 15.
In a clock cycle #1, at the rising edge of external clock signal extCLK, row address strobe signal /RAS is set at L level and column address strobe signal /CAS and write enable signal /WE are set at H level to apply an active command. Row related control circuit 9 shown in FIG. 13 is activated in accordance with the active command, and row selection circuit 3 performs row selection operation in accordance with internal row address signal X from address buffer 2 to drive a word line, corresponding to the row whose address has been designated, into a selected state. Row related control circuit 9 drives column related clock activation signal ENA into the active state in accordance with the active command. Column related clock activation signal ENA is driven into the active state in synchronization with the fall of internal clock signal CLK, and column related internal clock signal CLKD will be produced in clock cycles starting at next clock cycle #2.
The operation of these circuits are enabled by the production of column related internal clock signal CLKD to be applied to column related control circuit 10 and input/output control circuit 11 shown in FIG. 13.
In clock cycle #2, at the rising edge of external clock signal extCLK, row address strobe signal /RAS and write enable signal /WE are set at H level and column address strobe signal /CAS is set at L level to apply a read command. Column related control circuit 10 shown in FIG. 13 is activated in accordance with the read command to have an internal address signal from address buffer 2 applied to column selection circuit 4 as internal column address signal Y and to activate column selection circuit 4 for performing column selection operation for memory cell array 1. In addition, read control circuit 11a shown in FIG. 14 is activated in response to activation of read operation designation signal .phi.r from read command decoder 8a to activate preamplifier activation signal PAE to make preamplifier 6a perform amplification operation.
If CAS latency is now two, latency shifter 11b outputs data output designation signal OEMF applied from read control circuit 11a with one clock cycle delayed, so that data output activation signal OEM from latency shifter 11b is driven into the active state in a clock cycle #3, which is one clock cycle later than cloak cycle #2 in which the read command was applied.
The data amplified by preamplifier 6a is applied to an output buffer 6b, which in turn outputs the data from preamplifier 6a in clock cycle #3. Mask designation signal extDQM is in the inactive state at L level, internal mask designation signal DQMOT from mask control circuit 15 is at L level, and output enable signal OEMD from output control circuit 11c is driven into the active state in accordance with activation of data output activation signal OEM. This allows the reading of data from output buffer 6b in clock cycle #3. This initial data is brought into a defined state at the rising edge of external clock signal extCLK in a clock cycle #4.
Column selection circuit 4 (with reference to FIG. 13) selects a memory cell in every clock cycle in accordance with an address signal supplied from an internal burst address generator, for coupling to preamplifier 6a, from which the data from the selected memory cell is sequentially amplified to be applied to output buffer 6b.
In clock cycle #4, external mask designation signal extDQM is driven into the active state at H level at the rising edge of external clock signal extCLK. Responsively, mask designation signal DQMIN from DQM buffer 14 (with reference to FIG. 14) is brought into the active state at H level, and internal mask designation signal DQMOT from mask control circuit 15 is brought into the active state in a clock cycle #5 with one clock cycle delayed. Output control circuit 11c brings output enable signal OEMD into the inactive state at L level in accordance with activation of internal mask designation signal DQMOT. Thus, output buffer 6b is brought into the output high impedance state in clock cycle #5 to inhibit output of data.
External mask designation signal extDQM is in the active state only in clock cycle #4, and therefore internal mask designation signal DQMOT from mask control circuit 15 is again brought into the inactive state at L level in a next clock cycle #6, output enable signal OEMD is also again brought into the active state as data output activation signal OEM is in the active state, and output buffer 6b outputs the data applied from preamplifier 6a. The data output designation signal from read control circuit 11a is driven into the active state only for a period of four clock cycles as a burst length is four. Therefore, data output activation signal OEM from latency shifter 11b is also in the active state for a period of four clock cycles and brought into the inactive state at L level in a clock cycle #7, and responsively output enable signal OEMD is also brought into the inactive state at L level.
When the reading of all the necessary data is completed, in a clock cycle #8, row address strobe signal /RAS and write enable signal /WE are set at L level and column address strobe signal /CAS is set at H level to apply a precharge command for designating precharge for memory cell array 1. Thus, row related control circuit 9 drives column related clock activation signal ENA as well as row selection circuit 3 and the sense amplifier (with reference to FIG. 13) into the inactive state to bring memory cell array 1 back into a precharged state.
As described above, column related control circuit 10 and input/output control circuit 11 operate after the active command is applied and the memory cell array is brought into the active state (this is because data is written into/read out of the memory cell after a word line is selected). Thus, memory cell array 1 is activated and then column related internal clock signal CLKD is produced to be applied to these column related control circuit 10 and input/output control circuit 11 only for the period in which the column related circuits (column selection circuit 4 and input/output circuit 6) may operate, so as to reduce current consumption in these circuits.
The output data, which appears two clock cycles after external mask designation signal extDQM was applied, is masked. Even when external clock signal extCLK is in a high speed, it is ensured that the read out data has a sufficient time to be masked internally. The use of mask designation signal extDQM allows an external processor to read out only the data necessary for the processing, so that the need for selecting unwanted data in the internal portion of the processor is eliminated, thereby simplifying the processing operation.
FIG. 16A is a diagram showing an example of a structure of DQM buffer 14 shown in FIGS. 13 and 14. Referring to FIG. 16A, DQM buffer 14 includes: a transfer gate 14a formed of an n channel MOS transistor which is made conductive when an inversion clock signal /CLK of internal clock signal CLK is at H level, and allows passage of externally applied mask designation signal extDQM; cascaded two stage inverters 14b and 14c receiving the mask designation signal from transfer gate 14a; an inverter 14d forming a latch circuit with inverter 14b; and an AND circuit 14e receiving internal clock signal CLK and an output signal from inverter 14c to output mask designation signal DQMIN. Inverter 14d inverts an output signal from inverter 14b for transmission to the input of inverter 14b.
The operation of DQM buffer 14 shown in the FIG. 16A will now be described with reference to a timing chart shown in FIG. 16B.
Transfer gate 14a becomes conductive when internal clock signal CLK is at L level and passes externally applied mask designation signal extDQM. On the other hand, the transfer gate 14a becomes nonconductive when internal clock signal CLK is at H level, and external mask designation signal extDQM, applied when internal clock signal CLK is at L level, is latched by inverters 14b and 14d.
Now in a clock cycle #a, if external mask designation signal extDQM is set at H level, transfer gate 14a becomes conductive when internal clock signal CLK is at L level, and external mask designation signal extDQM at H Level is transmitted to inverter 14b to be latched by inverters 14b and 14d. In this state, internal clock signal CLK and mask designation signal DQMIN are both at L level.
When internal clock signal CLK rises to H level, transfer gate 14a becomes nonconductive and the external mask designation signal at H level is latched by inverters 14b and 14d. AND circuit 14e is enabled in synchronization with the rise of internal clock signal CLK, and raises mask designation signal DQMIN to H level in accordance with the signal at H level applied from inverter 14c. When internal clock signal CLK falls to L level, the mask designation signal from AND circuit 14e also falls; to L level.
Thus, external mask designation signal extDQM can be incorporated or latched in synchronization with internal clock signal CLK to produce mask designation signal DQMIN in synchronization with internal clock signal CLK.
FIG. 17A is a diagram exemplifying a structure of mask control circuit 15 shown in FIGS. 13 and 14. Referring to FIG. 17A, mask control circuit 15 includes cascaded three stage shift circuits 15a, 15b and 15c each delaying an applied signal by a half clock cycle of internal clock signal CLK for output. Shift circuit 15c has the same structure as that of shift circuit 15a, and is shown only in a block in FIG. 17A. Internal mask designation signal DQMOT is output from shift circuit 15c.
Shift circuit 15a includes: an NAND circuit 15aa receiving mask designation signal DQMIN and internal clock signal CLK; an NAND circuit 15ab receiving mask designation signal DQMIN supplied through inverter 15e and internal clock signal CLK; an NAND circuit 15ac receiving an output signal from NAND circuit 15aa at one input; and an NAND circuit 15ad receiving an output signal from NAND circuit 15ab at one input. An output signal from NAND circuit 15ad is applied to the other input of NAND circuit 15ac, while an output signal DQMO from NAND circuit 15ac is applied to the other input of NAND circuit 15ad. NAND circuits 15aa and 15ab each function as a transfer gate which is made conductive when internal clock signal CLK is at H level, and NAND circuits 15ac and 15ad constitute a latch circuit for latching an applied data signal.
Shift circuit 15b includes: an NAND circuit 15ab receiving internal clock signal /CLK and an output signal from NAND circuit 15ac; an NAND circuit 15bb receiving internal clock signal /CLK and an output signal from NAND circuit 15ad; an NAND circuit 15bc receiving an output signal from NAND circuit 15ba at one input; and an NAND circuit 15bb receiving an output signal from NAND circuit 15bb at one input. An output signal from NAND circuit 15bb is applied to the other input of NAND circuit 15bc, while an output signal from NAND circuit 15bc is applied to the other input of NAND circuit 15bd. Also in this shift circuit 15b, NAND circuits 15ba and 15bb have a function of a transfer gate which operates in accordance with internal clock signal /CLK, and NAND circuits 15bc and 15bd constitute a latch circuit for latching an applied signal. Now, the operation of the mask control circuit shown in FIG. 17A will be described with reference to a timing chart shown in FIG. 17B.
Mask designation signal DQMIN is at L level in a clock cycle #0. When internal clock signal CLK is at H level, in shift circuit 15a, NAND circuits 15aa and 15ab operate as inverters, so that the output signal from NAND circuit 15ad attains H level, and signal DQMO from NAND circuit 15ac responsibly attains L level. In shift circuit 15b, internal clock signal /CLK is at L level, whereas the output signals from NAND circuits 15ba and 15bb are at H level regardless of the output signal from shift circuit 15a. Thus, the state of output signal DQM1 from shift circuit 15b is not changed, maintaining L level in an initial state. Similarly, shift circuit 15c incorporates output signal DQM1 from shift circuit 15b, and internal mask designation signal DQMOT is at L level when internal clock signal CLK is at H level.
When internal clock signal CLK falls to L level, output signals from NAND circuits 15aa and 15ab in shift circuit 15a are fixed at H level, and shift circuit 15a is brought into a latching state. Shift circuit 15b incorporates output signal DQMO from shift circuit 15a when internal clock signal /CLK attains H level, and output signal DQM1 of shift circuit 15b is similarly fixed at L level. Shift circuit 15c is in the latching state as shift circuit 15a.
In clock cycle #1, mask designation signal DQMIN rises to H level. When internal clock signal CLK attains H level, in shift circuit 15a, NAND circuits 15aa and 15ab operate as inverters, the output signal from NAND circuit 15aa attains L level, and responsively signal DQMO from NAND circuit 15ac attains H level. Shift circuit 15b is in the latching state and the state of its output signal DQM1 is unchanged. Shift circuit 15c incorporates signal DQM1 to output internal mask designation signal DQMOT at L level.
When internal clock signal CLK falls to L level, shift circuit 15a is brought into the latching state and signal DQMO is retained at H level. In shift circuit 15b, NAND circuits 15ba and 15bb operate as inverters, and output signal DQM1 rises to H level in accordance with signal DQMO. As shift circuit 15c is in the latching state, internal mask designation signal DQMOT maintains L level.
In clock cycle #2, when internal clock signal CLK rises to H level again, shift circuit 15a incorporates mask designation signal DQMIN at L level and its output signal DQMO falls to L level. Shift circuit 15b is in the latching state and its output signal DQM1 retains H level. Shift circuit 15c incorporates signal DQM1 at H level and raises internal mask designation signal DQMOT, an output signal of shift circuit 15c, to H level.
In clock cycle #2, when internal clock signal CLK rises to L level, shift circuits 15a and 15c are brought into the latching state. Meanwhile, shift circuit 15b incorporates signal DQMO and falls its output signal DQM1 to L level. In clock cycle #3, when internal clock signal CLK rises to H level, shift circuit 15c incorporates signal DQM1 at L level from shift circuit 15b, and drives its internal mask designation signal DQMOT to L level. In this cycle, mask designation signal DQMIN is at L level and signals DQMO and DQM1 maintain L level. The same operation also happens in clock cycle #4.
The masking operation of mask control circuit 15 is related to the operation of the column related circuit, and preferably stopped when it is not necessary in terms of power consumption. On the other hand, operating mask control circuit 15 in accordance with column related internal clock signal CLKD results in a following problem.
A synchronous semiconductor memory device as shown in FIG. 18 is now considered in which CAS latency is one and an interval between an active command and a read command may be as short as one clock cycle, that is, an RAS-CAS precharge time in a standard DRAM may be one clock cycle. Column related internal clock signal CLKD is applied to mask control circuit 15 instead of internal clock signal CLK, different from the arrangement of FIG. 17A. Applying an active command in clock cycle #1 drives a column related clock activation signal ENA into the active state in clock cycle #1, and column related internal c-lock signal CLKD will be produced in clock cycles starting from clock cycle #2.
When a read command is applied in clock cycle #3, valid data is output from clock cycle #4. In clock cycle #4, when external mask designation signal extDQM is set in the active state, read out data is masked in clock cycle #6, two clock cycles after from clock cycle #4. The reading of data "2" is not therefore performed. After reading four data, external mask designation signal extDQM is reset at H level in a clock cycle #8. Clock activation signal ENA is driven into an inactive state as every operation of column related circuits related to column selection and data inputting/outputting is completed in clock cycle #8. Thus, in clock cycle #8, when column related internal clock signal CKD rises to H level and signals DQM0 and DQM1 attain H level, column related internal clock signal CLKD maintains L level in subsequent clock cycles, and shift circuits 15a and 15c are brought into the latching state. Signals DQMO and DQM1 from shift circuits 15a and 15c maintain H level and internal mask designation signal DQMOT maintains L level.
An active command is again applied in a clock cycle #10, column related clock activation signal ENA is brought into the active state, and a read command is applied in a clock cycle #11. L level of the clock signal CLKD is maintained in clock cycle #10 as column related internal clock signal CLKD has not yet been produced therein. In this state, signals DQM0 and DQM1 maintain H level, while internal mask designation signal DQMOT also maintains L level.
When column related internal clock signal CLKD is produced in a clock cycle #11, signal DQMO falls to L level, and in response to the fall of column related internal clock signal CLKD, signal DQM1 falls to L level. On the other hand, when column related internal clock signal CLKD is produced to attain H level, shift circuit 15c shown in FIG. 17A incorporates signal DQM1 at H level, so that internal mask designation signal DQMOT attains H level and falls to L level in a clock cycle #12. Thus, even when data output activation signal OEM is activated to attain H level in clock cycle #11, output enable signal OEMD maintains L level, and is not brought to H level until clock cycle #12. As a result, even when the reading of the data is performed with CAS latency of one by applying the read command in clock cycle #11, the initial data is unexpectedly masked, and therefore all the data except the initial data ("0") will be read out in clock cycles starting from a clock cycle #13.
In the synchronous semiconductor memory device, a user can set CAS latency at a suitable value in accordance with a system used. Given that the RAS-CAS delay time in the standard DRAM is elapsed, the read command can also be applied in a suitable timing. The timing at which the mask designation signal is brought into the active state to mask the read out data is suitably determined by the user in accordance with the content of processing, and therefore it cannot be predicted in advance. To satisfy these conditions, the mask control circuit cannot stop its operation even when the generation of column related internal clock signal CLKD is prohibited. Therefore the shift operation of the mask control circuit must be always performed, and internal clock signal CLK is applied to the mask control circuit as shown in FIG. 17A. The operation of masking the read out data however affects the circuitry only in the portion related to data inputting/outputting. Therefore, current consumption can be greatly reduced if the mask control circuit is operated in accordance with a column related clock signal and its operation can be stopped whenever it is not necessary.
Here, note that external mask designation signal extDQM is in the active state after reading out of the data is completed. This is because external mask designation signal extDQM is controlled such that it is set in the inactive state only when necessary data is read out in a process system. In other words, external mask designation signal extDQM enters the inactive state only when reading of data is necessary, and it is set in the active state to prohibit the data read out operation when the data needs not be read out. When such a control signal is used, it is apparent that external mask designation signal extDQM will be retained in the active state at H level when column related internal clock signal CLKD is not generated. As a result, the operation shown in FIG. 18 is performed, and therefore correct data cannot be read out.
Further, when a shift circuit is used, the current consumption for the shift circuit can be reduced by applying a clock signal only when the shift operation is necessary to operate the shift circuit. However, assume that, in such a shift circuit, an operation for its output signal is performed or predetermined control is performed in accordance with the output signal. If the internal state is retained as it is at the stop of the clock signal as long as the clock signal is kept stopped and if shift operation becomes necessary and the clock signal is applied, the signal latched upon the clock stop is output, thereby disadvantageously prohibiting generation of a correct output signal.